Hardware filtering is always required prior to digitization to prevent undesired signals and/or noise from being captured by the ADC(s). This anti-alias filtering is necessary to limit the signals presented to the ADC to the intended frequency range. Without such filtering (either through actual filtering circuitry or through band shaping of the various analog stages preceding the ADCs) the digital data stream is contaminated with either noise and/or spurious signals.
Software filtering is often required following digitization to select one or more desired signals from the captured data.
In the FPGA, the frequency translation (complex mixing with cos/sin) is performed before filtering and decimation, not the other way around. Thus, we get good attenuation of the other stations.
The decimation and lowpass filtering are combined. The decimator is currently built using a 4 stage CIC filter.
The frequency translation and sin/cos generation are implemented with the CORDIC algorithm. The decimating FIR filter is the 4 stage CIC filter.