Sunday, November 3, 2013

ABC of ADC(Analog to Digital Convertor)

ADC performance specifications are generally categorized in two ways: DC accuracy and dynamic performance.

Most applications use ADCs to measure a relatively static, DC-like signal (for example, a temperature sensor or strain-gauge voltage) or a dynamic signal (such as processing of a voice signal or tone detection). The application determines which specifications the designer will consider the most important.

DC accuracy
Many signals remain relatively static, such as those from temperature sensors or pressure transducers. In such applications, the measured voltage is related to some physical measurement, and the absolute accuracy of the voltage measurement is important. The ADC specifications that describe this type of accuracy are

offset error, 

full-scale error, 

differential nonlinearity (DNL), and 

integral nonlinearity (INL). 

These four specifications build a complete description of an ADC's absolute accuracy.

Although not a specification, one of the fundamental errors in ADC measurement is a result of the data-conversion process itself: quantization error. This error cannot be avoided in ADC measurements.

DC accuracy, and resulting absolute error are determined by four specs—offset, full-scale/gain error, INL, and DNL.

Quantization error is an artifact of representing an analog signal with a digital number (in other words, an artifact of analog-to-digital conversion). Maximum quantization error is determined by the resolution of the measurement (resolution of the ADC, or measurement if signal is oversampled). Further, quantization error will appear as noise, referred to as quantization noise in the dynamic analysis. For example, quantization error will appear as the noise floor in an FFT plot of a measured signal input to an ADC.

The ideal transfer function
The transfer function of an ADC is a plot of the voltage input to the ADC versus the code's output by the ADC. Such a plot is not continuous but is a plot of 2^N codes, where N is the ADC's resolution in bits.

If you were to connect the codes by lines (usually at code-transition boundaries), the ideal transfer function would plot a straight line. A line drawn through the points at each code boundary would begin at the origin of the plot, and the slope of the plot for each supplied ADC would be the same as shown in Figure below.




   
The transfer function can be implemented with an offset of - 1/2 LSB, as shown in Figure 2. This shift of the transfer function to the left shifts the quantization error from a range of (- 1 to 0 LSB) to (- 1/2 to +1/2 LSB).

  

Although this offset is intentional, it's often included in a data sheet as part of offset error.

Limitations in the materials used in fabrication mean that real-world ADCs won't have this perfect transfer function. It's these deviations from the perfect transfer function that define the DC accuracy and are characterized by the specifications in a data sheet.

The DC performance specifications described have accompanying figures that depict two transfer function segments: the ideal transfer function (solid, blue lines) and a transfer function that deviates from the ideal with the applicable error described (dashed, yellow line). This is done to better illustrate the meaning of the performance specifications.





The ideal transfer function line will intersect the origin of the plot. The first code boundary will occur at 1 LSB as shown in Figure 1. You can observe offset error as a shifting of the entire transfer function left or right along the input voltage axis, as shown above.

An error of - 1/2 LSB is intentionally introduced into some ADCs but is still included in the specification in the data sheet. Thus, the offset-error specification posted in the data sheet includes 1/2 LSB of offset by design. This is done to shift the potential quantization error in a measurement from 0 to 1 LSB to - 1/2 to +1/2 LSB. In this way, the magnitude of quantization error is intended to be < 1/2 LSB, as Figure below illustrates.



Full-scale error is the difference between the ideal code transition to the highest output code and the actual transition to the output code when the offset error is zero. This is observed as a change in slope of the transfer function line as shown in Figure below. A similar specification, gain error, also describes the nonideal slope of the transfer function as well as what the highest code transition would be without the offset error. Full-scale error accounts for both gain and offset deviation from the ideal transfer function. Both full-scale and gain errors are commonly used by ADC manufacturers.


Nonlinearity
Ideally, each code width (LSB) on an ADC's transfer function should be uniform in size. For example, all codes in Figure 2 should represent exactly 1/8th of the ADC's full-scale voltage reference. The difference in code widths from one code to the next is differential nonlinearity (DNL). The code width (or LSB) of an ADC is shown in Equation below



The voltage difference between each code transition should be equal to one LSB.

Deviation of each code from an LSB is measured as DNL. This can be observed as uneven spacing of the code "steps" or transition boundaries on the ADC's transfer-function plot.

 In Figure below, a selected digital output code width is shown as larger than the previous code's step size. This difference is DNL error. DNL is calculated as shown in Equation below.





The integral nonlinearity (INL) is the deviation of an ADC's transfer function from a straight line.

This line is often a best-fit line among the points in the plot but can also be a line that connects the highest and lowest data points, or endpoints.

 INL is determined by measuring the voltage at which all code transitions occur and comparing them to the ideal.

The difference between the ideal voltage levels at which code transitions occur and the actual voltage is the INL error, expressed in LSBs.

 INL error at any given point in an ADC's transfer function is the accumulation of all DNL errors of all previous (or lower) ADC codes, hence it's called integral nonlinearity.

This is also observed as the deviation from a straight-line transfer function, as shown in Figure below.


Because nonlinearity in measurement will cause distortion, INL will also affect the dynamic performance of an ADC.

Absolute error
The absolute error is the total DC measurement error and is characterized by the offset, full-scale, INL, and DNL errors. Quantization error also affects accuracy, but it's inherent in the analog-to-digital conversion process (and so does not vary from one ADC to another of equal resolution).

When designing with an ADC, the engineer uses the performance specifications posted in the data sheet to calculate the maximum absolute error that can be expected in the measurement, if it's important.

Offset and full-scale errors can be reduced by calibration at the expense of dynamic range and the cost of the calibration process itself.

Offset error can be minimized by adding or subtracting a constant number to or from the ADC output codes.

Full-scale error can be minimized by multiplying the ADC output codes by a correction factor.

Dynamic performance
An ADC's dynamic performance is specified using parameters obtained via frequency-domain analysis and is typically measured by performing a fast Fourier transform (FFT) on the output codes of the ADC.

 In Figure below, the fundamental frequency is the input signal frequency.

This is the signal measured with the ADC. Everything else is noise—the unwanted signals—to be characterized with respect to the desired signal.

This includes harmonic distortion, thermal noise, 1/ƒ noise, and quantization noise.

Engineers minimize outside sources of error when assessing the performance of an ADC and in their system design.



Signal-to-noise ratio
The signal-to-noise ratio (SNR) is the ratio of the root mean square (RMS) power of the input signal to the RMS noise power (excluding harmonic distortion), expressed in decibels (dB), as shown in Equation below.



The noise measured in an SNR calculation doesn't include harmonic distortion but does include quantization noise (an artifact of quantization error) and all other sources of noise (for example, thermal noise).

This noise floor is depicted in the FFT plot in Figure below.

For a given ADC resolution, the quantization noise is what limits an ADC to its theoretical best SNR because quantization error is the only error in an ideal ADC.



 

The theoretical best SNR is calculated in Equation below.

SNR(dB)=6.02N+1.76

Where N is the ADC resolution

Quantization noise can only be reduced by making a higher-resolution measurement (in other words, a higher-resolution ADC or oversampling). Other sources of noise include thermal noise, 1/ƒ noise, and sample clock jitter.

Harmonic distortion

Nonlinearity in the data converter results in harmonic distortion when analyzed in the frequency domain. Such distortion is observed as "spurs" in the FFT at harmonics of the measured signal as illustrated in Figure 10. This distortion is referred to as total harmonic distortion (THD), and its power is calculated in Equation below.






The magnitude of harmonic distortion diminishes at high frequencies to the point that its magnitude is less than the noise floor or is beyond the bandwidth of interest.

 Data sheets typically specify to what order the harmonic distortion has been calculated. Manufacturers will specify which harmonic is used in calculating THD; for example, up to the fifth harmonic is common.

Signal-to-noise and distortion
Signal-to-noise and distortion (SiNAD) offers a more complete picture by including the noise and harmonic distortion in one specification. SiNAD gives a description of how the measured signal will compare to the noise and distortion. You can calculate the SiNAD ratio using Equation below.



Spurious-free dynamic range
Finally, spurious-free dynamic range (SFDR) is the difference between the magnitude of the measured signal and its highest spur peak. This spur is typically a harmonic of the measured signal but doesn't have to be. SFDR is shown in Figure below





Source : http://www.embedded.com/design/configurable-systems/4025078/Understanding-analog-to-digital-converter-specifications

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