Wednesday, April 24, 2013

Important about USRP FPGA images and DDC Filters (CIC + HBF)

USRP-1 has two fpga images :

One with half-band filters and another one without half-and filters.

The fpga file with half-band filter is

usrp1_fpga.rbf located in /usr/local/share/uhd/images

USRP1 cannot achieve decimations below 8 when the half-band filter is present.

This means you cant get samples more than 8 MSPS in the CPU when the half-bad filters are present because actual rate at which CPU receives samples is  adc_rate/decim_rate i.e. 64MSPS/decim_rate , so if decim_rate >=8
this implies samples per sec to CPU <= 8MHz and hence we wont be able to see more than 8MHz

The another image i.e. usrp1_fpga_4rx.rbf file is a special FPGA image without RX half-band filters.
To load this image, set the device address key/value pair: fpga=usrp1_fpga_4rx.rbf

uhd_fft -a "fpga=usrp1_fpga_4rx.rbf"

Even after using this fpga image you wont get samples more than 16MSPS to the CPU

If you try to go above , it will get back to 16MSPS only,

So this means no decimation less than 4 is possible in any of the current FPGA images.

** Keep in mind that if you use this image then there is no low pass filtering by the half-band filter. Low pass filtering is essentially required after decimation. So in this case you have to do low pass filtering in software by yourself. 

** uhd set_samp_rate never fails; always falls back to closest requested

** If the USRP DDC decimation rate is X. The CIC filter response (decimation =Y ), HBF response (decimation =Z) and cascaded CIC + HBF (total decimation =Y*Z ) i.e. X is actually Y*Z ... Since DDC is implemented with CIC and half-band filters !!

** But for the another image i.e. without half-band filter, the total decimation = Y only

** CIC decimator is a fourth order filter here

Details about CIC decimator can be found in


** Half-band filter is 31 tap

The coefficients of the Half-band are symmetric, and with the exception of the middle tap, every other coefficient is zero.  The middle section of taps looks like this:

  ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468,                                                                   |
                                        middle tap -------+
Details about its implementation can be found in


One interesting discussion :

Reference :

Is there away to disable (or bypass) the USRP FPGA DDC half band filter? I want to get the samples directly from the CIC decimation filter and do the low pass filtering by software. I developed a MATLAB based professional 100KHz bandwidth digital down converter as shown in the attached m file. I want to test this design in USRP. In the mean time, I cannot do this because I don't have access to the CIC output samples because of the HBF.
Waiting for your help, thank you.


If receive only is OK, you can use the "fpga=usrp1_fpga_4rx.rbf" configuration



A very nice discussion about frequency response of the various filters involved in the DDC stages.

Reference :

USRP CIC Frequency Response :
USRP CIC Frequency Response Zoomed :
USRP half-band Filter Frequency Response :

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