Wednesday, April 24, 2013

Beamforming with SDR

** The information/content below has been taken form a technical literature at PENTEK Inc.

Beamforming is a signal processing technique that utilizes an array of sensors to achieve directionality, increase the strength of transmitted signals and improve the quality of received signals. For software radio systems, the beamforming sensors are transmit and receive antennas. For receiver systems, the signal arrival delay at each antenna is directly proportional to the path distance from the source. The beamforming process adjusts the gain and phase of each antenna signal to cancel the delay path differences for signals arriving from a particular direction. Aligned signals are then summed together to produce high signal-to-noise reception in the chosen direction. By adjusting gain and phase in each path, the antenna is electronically “steered” without the need for moving mechanical structures.

Examples of software radio applications that use beamforming include direction finding, in which a beamformed antenna can be steered to locate the arrival angle of a signal source. Two or more arrays can be used to triangulate the exact location of the source, which is essential for many signal intelligence. In addition to directionality, beamforming also improves reception in so-called “diversity receivers”. The combined signal from multiple antennas boosts the signal-to-noise ratio compared to a single antenna, thus extending the operational range of the receiver system. And lastly, beamforming allows spatial frequency sharing for commercial mobile phone carriers by dividing one cell into several beamformed pie-slice sectors that can share the same frequency.

FPGAs are best suited for processing-intensive digital signal processing algorithms, especially like those found in beamforming applications. They can implement extreme parallelism with hundreds of DSP blocks operating in parallel. The key signal processing elements for beamforming include digital down conversion, phase and gain adjustments, and summation, all handled by the DSP engines. The PCIe interface provides a fast interface to the system controller for initialization and delivery of beamforming coefficients for gain and phase shifts. The gigabit serial links also can be extremely useful in propagating the beamformed summation across multiple boards for high channel count systems. The configurable logic supports timing synchronization across the channels and data formatting.

 Basic signal processing tasks required for beamforming :

1. The RF signals from the antenna must first be amplified and translated to an IF (intermediate frequency) signal to permit digitization by the A/D converter.

2. Popular IF frequencies range from 21.4 to 160 MHz and many A/D converters now handle these signals with sampling rates between 80 and 500 Msamples/sec.

3. These high-speed A/D converters connect directly to FPGAs with high speed LVDS interfaces supporting data converter peripherals operating at sample rates to 600 MHz and higher.

4. The next task is digital downconver sion of the IF signal to baseband, producing a complex (I+Q) signal centered at DC or 0 Hz.

5. The downconverted baseband signal is low-pass filtered to allow only the signal of interest to appear at the output. Together, these operations represent the classic software radio function — the DDC.

6. Inside the DDC, the frequency translation to baseband is performed by mixing the digital A/D input signal with digital samples from a numerically controlled local oscillator (NCO).

7. The mixer employs two multipliers from the FPGA DSP blocks to handle the real A/D samples and the complex NCO samples. The NCO is a phase accumulator (also part of the DSP block) followed by a sine look-up table. The table converts the steadily advancing phase value to sine wave samples. The NCO frequency is programmable by the operator to produce any frequency from DC to the A/D sample clock frequency.

8. The complex baseband signal at the mixer output is fed into a low pass filter using DSP block multipliers, registers and adders. It features programmable filter coefficients to set the signal channel bandwidth. Special circuitry incorporated in the NCO allows the user to offset the phase accumulator by a programmable angle to implement the phase shift requirement for beamforming.

9. The gain adjustment is performed using a DSP block multiplier.

10. Finally, the adjusted outputs of each DDC are summed together, again taking advantage of adders in the DSP blocks.

** Gain and phase adjustments are performed by the DDC which is inside the FPGA itself.

** power meters at the output of the DDC are required to measure the output power in case of any recalibration of the gain settings.

** Role of FPGA (summarized) :

1. digital downconversion
2. synchronization and timing
3. phase and gain adjustments
4. power measurement
5. summation
6. gigabit serial links for summation propagation
7. the PCIe system interface for control
8. high speed interfaces to A/Ds and other peripheral devices.

Recently Ettus Research has also came up with a product "Quad Receiver QR210" which is capable of beam forming. Same can be seen in this informative video 

More information about QR210 can be found at

Additionally there are a whole lot of FPGA boards from PENTEK ( which are capable to do beamforming.

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